The Card Services ParseTuple
function interprets raw CIS tuple
data from a call to GetTupleData
and returns the tuple contents
in a form dependant on the tuple type. This section describes the
parsed tuple contents.
#include "cistpl.h"
The cistpl_checksum_t
structure is given by:
typedef struct cistpl_checksum_t {
u_short addr;
u_short len;
u_char sum;
} cistpl_checksum_t;
The cistpl_longlink_t
structure is given by:
typedef struct cistpl_longlink_t {
u_int addr;
} cistpl_longlink_t;
These tuples are pointers to additional chains of CIS tuples, either
in attribute or common memory. Each CIS tuple chain can have at most
one long link. CISTPL_LONGLINK_A
tuples point to attribute
memory, and CISTPL_LONGLINK_C
tuples point to common memory. The
standard CIS chain starting at address 0 in attribute memory has an
implied long link to address 0 in common memory. A CISTPL_NOLINK
tuple can be used to cancel this default link.
The first tuple of a chain pointed to by a long link must be a
CISTPL_LINKTARGET
. The CS tuple handling code will automatically
follow long links and verify link targets; these tuples are
normally invisible unless the TUPLE_RETURN_LINK
attribute is
specified in GetNextTuple
.
The cistpl_longlink_mfc_t
structure is given by:
typedef struct cistpl_longlink_mfc_t {
int nfn;
struct {
u_char space;
u_int addr;
} fn[CISTPL_MAX_FUNCTIONS;
} cistpl_longlink_mfc_t;
This tuple identifies a multifunction card, and specifies long link
pointers to CIS chains specific for each function. The space
field is either CISTPL_MFC_ATTR
or CISTPL_MFC_COMMON
for
attribute or common memory space.
The cistpl_device_t
structure is given by:
typedef struct cistpl_device_t {
int ndev;
struct {
u_char type;
u_char wp;
u_int speed;
u_int size;
} dev[CISTPL_MAX_DEVICES];
} cistpl_device_t;
The CISTPL_DEVICE
tuple describes address regions in a card's
common memory. The CISTPL_DEVICE_A
tuple describes regions in
attribute memory. The type
flag indicates the type of memory
device for this region. The wp
flag indicates if this region is
write protected. The speed
field is in nanoseconds, and
size
is in bytes. Address regions are assumed to be ordered
consecutively starting with address 0. The following device types are
defined:
CISTPL_DTYPE_NULL
Specifies that there is no device, or a ``hole'' in the card address space.
CISTPL_DTYPE_ROM
Masked ROM
CISTPL_DTYPE_OTPROM
One-type programmable ROM.
CISTPL_DTYPE_EPROM
UV erasable PROM.
CISTPL_DTYPE_EEPROM
Electrically erasable PROM.
CISTPL_DTYPE_FLASH
Flash EPROM.
CISTPL_DTYPE_SRAM
Static or non-volatile RAM.
CISTPL_DTYPE_DRAM
Dynamic or volatile RAM.
CISTPL_DTYPE_FUNCSPEC
Specifies a function-specific device, such as a memory-mapped IO device or buffer, as opposed to general purpose storage.
CISTPL_DTYPE_EXTEND
Specifies an extended device type. This type is reserved for future use.
The cistpl_vers_1_t
structure is given by:
typedef struct cistpl_vers_1_t {
u_char major;
u_char minor;
int ns;
int ofs[CISTPL_VERS_1_MAX_PROD_STRINGS];
char str[254];
} cistpl_vers_1_t;
The ns
field specifies the number of product information strings
in the tuple. The string data is contained in the str
array. Each
string is null terminated, and ofs
gives the offset to the start
of each string.
The cistpl_altstr_t
structure is given by:
typedef struct cistpl_altstr_t {
int ns;
int ofs[CISTPL_ALTSTR_MAX_STRINGS];
char str[254];
} cistpl_altstr_t;
The ns
field specifies the number of alternate language strings
in the tuple. The string data is contained in the str
array. Each
string is null terminated, and ofs
gives the offset to the start
of each string.
The cistpl_jedec_t
structure is given by:
typedef struct cistpl_jedec_t {
int nid;
struct {
u_char mfr;
u_char info;
} id[CISTPL_MAX_DEVICES];
} cistpl_jedec_t;
JEDEC identifiers describe the specific device type used to implement
a region of card memory. The nid
field specifies the number of
JEDEC identifiers in the tuple. There should be a one-to-one
correspondence between JEDEC identifiers and device descriptions in
the corresponding CISTPL_DEVICE
tuple.
The cistpl_config_t
structure is given by:
typedef struct cistpl_config_t {
u_char last_idx;
u_int base;
u_int rmask[4];
u_char subtuples;
} cistpl_config_t;
The last_idx
field gives the index of the highest numbered
configuration table entry. The base
field gives the offset of a
card's configuration registers in attribute memory. The rmask
array is a series of bit masks indicating which configuration
registers are present. Bit 0 of rmask[0]
is for the COR, bit 1
is for the CCSR, and so on. The subtuples
field gives the number
of bytes of subtuples following the normal tuple contents.
For CISTPL_CONFIG_CB
, rmask
is undefined, and base
points to the CardBus status registers.
The cistpl_bar_t
structure is given by:
typedef struct cistpl_bar_t {
u_char attr;
u_int size;
} cistpl_long_t;
A CISTPL_BAR
tuple describes the characteristics of an address
space region pointed to by a PCI base address register, for CardBus
cards.
The following bit fields are defined in attr
:
CISTPL_BAR_SPACE
Identifies the base address register, from 1 to 6. A value of 7 describes the card's Extension ROM space.
CISTPL_BAR_SPACE_IO
If set, this address register maps IO space (as opposed to memory space).
CISTPL_BAR_PREFETCH
If set, this region can be prefetched. controller.
CISTPL_BAR_CACHEABLE
If set, this region is cacheable as well as prefetchable.
CISTPL_BAR_1MEG_MAP
If set, this region should only be mapped into the first 1MB of the host's physical address space.
The cistpl_cftable_entry_t
structure is given by:
typedef struct cistpl_cftable_entry_t {
u_char index;
u_char flags;
u_char interface;
cistpl_power_t vcc, vpp1, vpp2;
cistpl_timing_t timing;
cistpl_io_t io;
cistpl_irq_t irq;
cistpl_mem_t mem;
u_char subtuples;
} cistpl_cftable_entry_t;
A CISTPL_CFTABLE_ENTRY
structure describes a complete operating
mode for a card. Many sections are optional. The index
field
gives the configuration index for this operating mode; writing this
value to the card's Configuration Option Register selects this mode.
The following fields are defined in flags
:
CISTPL_CFTABLE_DEFAULT
Specifies that this is the default configuration table entry.
CISTPL_CFTABLE_BVDS
Specifies that this configuration implements the BVD1 and BVD2 signals in the Pin Replacement Register.
CISTPL_CFTABLE_WP
Specifies that this configuration implements the write protect signal in the Pin Replacement Register.
CISTPL_CFTABLE_RDYBSY
Specifies that this configuration implements the Ready/Busy signal in the Pin Replacement Register.
CISTPL_CFTABLE_MWAIT
Specifies that the WAIT
signal should be observed during memory
access cycles.
CISTPL_CFTABLE_AUDIO
Specifies that this configuration generates an audio signal that can be routed to the host system speaker.
CISTPL_CFTABLE_READONLY
Specifies that the card has a memory region that is read-only in this configuration.
CISTPL_CFTABLE_PWRDOWN
Specifies that this configuration supports a power down mode, via the Card Configuration and Status Register.
The cistpl_power_t
structure is given by:
typedef struct cistpl_power_t {
u_char present;
u_char flags;
u_int param[7];
} cistpl_power_t;
The present
field is bit mapped and indicates which parameters
are present for this power signal. The following indices are defined:
CISTPL_POWER_VNOM
The nominal supply voltage.
CISTPL_POWER_VMIN
The minimum supply voltage.
CISTPL_POWER_VMAX
The maximum supply voltage.
CISTPL_POWER_ISTATIC
The continuous supply current required.
CISTPL_POWER_IAVG
The maximum current averaged over one second.
CISTPL_POWER_IPEAK
The maximum current averaged over 10 ms.
CISTPL_POWER_IDOWN
The current required in power down mode.
Voltages are given in units of 10 microvolts. Currents are given in units of 100 nanoamperes.
The cistpl_timing_t
structure is given by:
typedef cistpl_timing_t {
u_int wait, waitscale;
u_int ready, rdyscale;
u_int reserved, rsvscale;
} cistpl_timing_t;
Each time consists of a base time in nanoseconds, and a scale multiplier. Unspecified times have values of 0.
The cistpl_io_t
structure is given by:
typedef struct cistpl_io_t {
u_char flags;
int nwin;
struct {
u_int base;
u_int len;
} win[CISTPL_IO_MAX_WIN;
} cistpl_io_t;
The number of IO windows is given by nwin
. Each window is
described by a base address, base
, and a length in bytes,
len
. The following bit fields are defined in flags
:
CISTPL_IO_LINES_MASK
The number of IO lines decoded by this card.
CISTPL_IO_8BIT
Indicates that the card supports split 8-bit accesses to 16-bit IO registers.
CISTPL_IO_16BIT
Indicates that the card supports full 16-bit accesses to IO registers.
The cistpl_irq_t
structure is given by:
typedef struct cistpl_irq_t {
u_int IRQInfo1;
u_int IRQInfo2;
} cistpl_irq_t;
The following bit fields are defined in IRQInfo1
:
IRQ_MASK
A specific interrupt number that this card should use.
IRQ_NMI_ID
, IRQ_IOCK_ID
, IRQ_BERR_ID
,
IRQ_VEND_ID
When IRQ_INFO2_VALID
is set, these indicate if a corresponding
special interrupt signal may be assigned to this card. The four flags
are for the non-maskable, IO check, bus error, and vendor specific
interrupts.
IRQ_INFO2_VALID
Indicates that IRQInfo2
contains a valid bit mask of allowed
interrupt request numbers.
IRQ_LEVEL_ID
Indicates that the card supports level mode interrupts.
IRQ_PULSE_ID
Indicates that the card supports pulse mode interrupts.
IRQ_SHARE_ID
Indicates that the card supports sharing interrupts.
If IRQInfo1
is 0, then no interrupt information is available.
The cistpl_mem_t
structure is given by:
typedef struct cistpl_mem_t {
u_char nwin;
struct {
u_int len;
u_int card_addr;
u_int host_addr;
} win[CISTPL_MEM_MAX_WIN;
} cistpl_mem_t;
The number of memory windows is given by nwin
. Each window is
described by an address in the card memory space, card_addr
, an
address in the host memory space, host_addr
, and a length in
bytes, len
. If the host address is 0, the position of the window
is arbitrary.
The cistpl_cftable_entry_cb_t
structure is given by:
typedef struct cistpl_cftable_entry_cb_t {
u_char index;
u_char flags;
cistpl_power_t vcc, vpp1, vpp2;
u_char io;
cistpl_irq_t irq;
u_char mem;
u_char subtuples;
} cistpl_cftable_entry_cb_t;
A CISTPL_CFTABLE_ENTRY_CB
structure describes a complete
operating mode for a CardBus card. Many fields are identical to
corresponding fields in CISTPL_CFTABLE_ENTRY
.
The io
and mem
fields specify which base address registers
need to be initialized for this configuration. Bits 1 through 6
correspond to the six base address registers, and bit 7 indicates the
expansion ROM base register.
The cistpl_manfid_t
structure is given by:
typedef struct cistpl_manfid_t {
u_short manf;
u_short card;
} cistpl_manfid_t;
The manf
field identifies the card manufacturer. The card
field is chosen by the vendor and should identify the card type and
model.
The cistpl_funcid_t
structure is given by:
typedef struct cistpl_funcid_t {
u_char func;
u_char sysinit;
} cistpl_funcid_t;
The func
field identifies the card function. The sysinit
field contains several bit-mapped flags describing how the card should
be configured at boot time.
The following functions are defined:
CISTPL_FUNCID_MULTI
A multi-function card.
CISTPL_FUNCID_MEMORY
A simple memory device.
CISTPL_FUNCID_SERIAL
A serial port or modem device.
CISTPL_FUNCID_PARALLEL
A parallel port device.
CISTPL_FUNCID_FIXED
A fixed disk device.
CISTPL_FUNCID_VIDEO
A video interface.
CISTPL_FUNCID_NETWORK
A network adapter.
CISTPL_FUNCID_AIMS
An auto-incrementing mass storage device.
The following flags are defined in sysinit
:
CISTPL_SYSINIT_POST
Indicates that the system should attempt to configure this card during its power-on initialization.
CISTPL_SYSINIT_ROM
Indicates that the card contains a system expansion ROM that should be configured at boot time.
The cistpl_device_geo_t
structure is given by:
typedef struct cistpl_device_geo_t {
int ngeo;
struct {
u_char buswidth;
u_int erase_block;
u_int read_block;
u_int write_block;
u_int partition;
u_int interleave;
} geo[CISTPL_MAX_DEVICES];
} cistpl_device_geo_t;
The erase_block
, read_block
, and write_block
sizes are
in units of buswidth
bytes times interleave
. The
partition
size is in units of erase_block
.
The cistpl_vers_2_t
structure is given by:
typedef struct cistpl_vers_2_t {
u_char vers;
u_char comply;
u_short dindex;
u_char vspec8, vspec9;
u_char nhdr;
int vendor, info;
char str[244];
} cistpl_vers_2_t;
The vers
field should always be 0. The comply
field
indicates the degree of standard compliance and should also be 0. The
dindex
field reserves the specified number of bytes at the start
of common memory. The vspec8
and vspec9
fields may contain
vendor-specific information. The nhdr
field gives the number of
copies of the CIS that are present on this card. The str
array
contains two strings: a vendor name, and an informational message
describing the card. The offset of the vendor string is given by
vendor
, and the offset of the product info string is in
info
.
The cistpl_org_t
structure is given by:
typedef struct cistpl_org_t {
u_char data_org;
char desc[30];
This tuple describes the data organization of a memory partition. The
following values are defined for data_org
:
CISTPL_ORG_FS
The partition contains a filesystem.
CISTPL_ORG_APPSPEC
The partition is in an application specific format.
CISTPL_ORG_XIP
The partition follows the Execute-In-Place specification.
The desc
field gives a text description of the data organization.
The cistpl_format_t
structure is given by:
typedef struct cistpl_org_t {
u_char type;
u_char edc;
u_int offset;
u_int length;
This tuple describes the data recording format for a memory region.
The following values are defined for type
:
CISTPL_FORMAT_DISK
The partition uses a disk-like format.
CISTPL_FORMAT_MEM
The partition uses a memory-like format.
The following values are defined for edc
:
CISTPL_EDC_NONE
No error detection code is used.
CISTPL_EDC_CKSUM
Each block has a one-byte arithmetic checksum.
CISTPL_EDC_CRC
Each block has a two-byte cyclic redundancy check.
CISTPL_EDC_PCC
The entire partition has a one-byte checksum.
The offset
field specifies the address of the first data byte,
and length
specifies the total number of data bytes in this
partition.
The PC Card standard defines a few standard configuration registers
located in a card's attribute memory space. A card's CONFIG
tuple specifies which of these registers are implemented. Programs
using these definitions should include:
#include "cisreg.h"
This register should be present for virtually all IO cards. Writing to this register selects a configuration table entry and enables a card's IO functions.
The following bit fields are defined:
COR_CONFIG_MASK
Specifies the configuration table index describing the card's current operating mode.
COR_LEVEL_REQ
Specifies that the card should generate level mode (edge-triggered) interrupts, the default.
COR_SOFT_RESET
Setting this bit performs a ``soft'' reset operation. Drivers should
use the ResetCard
call to reset a card, rather than writing
directly to this register.
The following bit fields are defined:
CCSR_INTR_ACK
If this bit is set, then the CCSR_INTR_PENDING
bit will remain
set until it is explicitly cleared.
CCSR_INTR_PENDING
Signals that the card is currently asserting an interrupt request. This signal may be helpful for supporting interrupt sharing.
CCSR_POWER_DOWN
Setting this bit signals that the card should enter a power down state.
CCSR_AUDIO_ENA
Specifies that the card's audio output should be enabled.
CCSR_IOIS8
This is used by the host to indicate that it can only perform 8-bit IO operations and that 16-bit accesses will be carried out as two 8-bit accesses.
CCSR_SIGCHG_ENA
This indicates to the card that it should use the SIGCHG
signal
to indicate changes in the WP
, READY
, BVD1
, and
BVD2
signals.
CCSR_CHANGED
This bit signals to the host that one of the signals in the Pin Replacement Register has changed state.
Signals in this register replace signals that are not available when a
socket is operating in memory and IO mode. An IO card will normally
assert the SIGCHG
signal to indicate that one of these signals
has changed state, then a driver can poll this register to find out
specifically what happened.
The following bit fields are defined:
PRR_WP_STATUS
The current state of the write protect signal.
PRR_READY_STATUS
The current state of the ready signal.
PRR_BVD2_STATUS
The current state of the battery warn signal.
PRR_BVD1_STATUS
The current state of the battery dead signal.
PRR_WP_EVENT
Indicates that the write protect signal has changed state since the PRR register was last read.
PRR_READY_EVENT
Indicates that the ready signal has changed state since the PRR register was last read.
PRR_BVD2_EVENT
Indicates that the battery warn signal has changed state since the PRR register was last read.
PRR_BVD1_EVENT
Indicates that the battery dead signal has changed state since the PRR register was last read.
This register can also be written. In this case, the STATUS
bits
act as a mask; if a STATUS
bit is set, the corresponding
EVENT
bit is updated by the write.
This register is used when several identical cards may be set up to share the same range of IO ports, to emulate an ISA bus card that would control several devices. For example, an ISA hard drive controller might control several drives, selectable by writing a drive number to an IO port. For several card drives to emulate this controller interface, each needs to ``know'' which drive it is, so that it can identify which IO operations are intended for it.
The following bit fields are defined:
SCR_SOCKET_NUM
This should indicate the socket number in which the card is located.
SCR_COPY_NUM
If several identical cards are installed in a system, this field should be set to a unique number identifying which of the identical cards this is.
The following bit fields are defined:
ESR_REQ_ATTN_ENA
When set, the CCSR_CHANGED
bit will be set when the
ESR_REQ_ATTN
bit is set, possibly generating a status change
interrupt.
ESR_REQ_ATTN
Signals a card event, such as an incoming call for a modem.
For multifunction cards, these registers are used to tell the card how
the host IO windows have been configured for each card function.
There are four IO Base registers, from CISREG_IOBASE_0
to
CISREG_IOBASE_3
, for the low-order through high-order bytes of an
IO address up to 32 bits long. The CISREG_IOSIZE
register is
supposed to be written as the number of IO ports allocated, minus
one. For MFC-compliant cards, Card Services will automatically set
all of these registers when RequestConfiguration
is called.